Join our team!

We have a collaborative, respectful, open and fun culture, coupled with a mission driven mentality as we work towards building an iconic, enduring high technology company.

Full Time
Frontend RTL Design Engineer

Why join Auradine? You want to be a part of something groundbreaking, where every day you can see the impact of your work. At Auradine, you will join a talent-rich group of problem solvers and doers; in a culture that focuses on team, growth, innovation, and creativity

Job Responsibilities:

  • As a member of the Custom ASIC Design team, you will help define and document micro-architecture on next generation designs. Responsible for the logic design/RTL entry and timing closure in a high-performance custom CPU and/or logic Core.
  • Interface with physical design, design for test, power, and performance modeling teams to optimize tradeoffs within the design. Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent.
  • Mentor junior team members and summer interns and cultivate a growth mindset among the team to encourage collaboration and inclusion.


  • Candidates must have at least a bachelor’s degree in electrical engineering, computer engineering, computer science, or a related degree or equivalent work experience.
  • 9+ years of related technical engineering experience.
  • 5+ years of industry experience in logic design with a proven record of accomplishment of delivering complex CPU, GPU or SoC IP’s.
  • Solid background and understanding of computer architecture.
  • Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
  • Able to thrive or lead in a fast-paced startup environment.


  • 8+ years of industry experience in logic design.
  • 5+ years working on complex CPU architectures.
  • Experience/Specialization in one or more of the following areas: instruction set definition, hardware/software partition, on chip caches/memory, Integer, and floating-point arithmetic, ALU operations, deeply pipelined designs, coherent subsystem design, bus interface including industry standard bus protocols and memory ordering models.
  • Substantial background in debugging designs as well as simulation environments.
  • Experience with digital timing analysis, multiple clocks, power, synthesis, place-n-route.
  • Knowledge of verification principles, testbenches, UVM, and coverage. Scripting languages such as Python or Perl.
  • Crypto or blockchain computing experience is a big plus.

At Auradine:

Our goal is to hire and promote an exceptional workforce as diverse as the global populations we serve. Auradine, is an equal opportunity employer committed to diversity, inclusion, and belonging in all aspects of our organization. We value and celebrate diversity in thought, beliefs, talent, expression, and backgrounds. We know that our individual differences make us better. Come join us!


The national pay range for our technical roles is $100,000-$500,000. The national pay range for our non-technical roles is $75,000-$470,000. Individual compensation will be commensurate with the candidate’s experience aligned with Auradine’s internal leveling guidelines and benchmarks.

Auradine is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.

Auradine is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or reasonable accommodation for any part of the application or hiring process may contact us at: careers This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case-by-case basis.

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